<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>1846317</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Sun Jul 22 21:09:30 2018</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2017.1 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>e1f10f10a8184f5b8e98b7d161bbcd6f</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>25</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>603a3fa3-7bc9-4e04-b1ad-e9fd483915f3</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>603a3fa3-7bc9-4e04-b1ad-e9fd483915f3</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7k325t</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>kintex7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>ffg900</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-2</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i3-3240 CPU @ 3.40GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3392 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 7 , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>Service Pack 1  (build 7601)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_resources</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addilaprobespopup_ok=4</TD>
   <TD>addsrcwizard_specify_hdl_netlist_block_design=3</TD>
   <TD>addsrcwizard_specify_or_create_constraint_files=1</TD>
   <TD>addsrcwizard_specify_simulation_specific_hdl_files=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_apply=4</TD>
   <TD>basedialog_cancel=3</TD>
   <TD>basedialog_no=1</TD>
   <TD>basedialog_ok=343</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_yes=18</TD>
   <TD>cfgmempartchooser_density_chooser=4</TD>
   <TD>cfgmempartchooser_manufacturer_chooser=2</TD>
   <TD>cfgmempartchooser_table=38</TD>
</TR><TR ALIGN='LEFT'>   <TD>cfgmempartchooser_type_chooser=4</TD>
   <TD>cfgmempartchooser_width_chooser=2</TD>
   <TD>cmdmsgdialog_messages=16</TD>
   <TD>cmdmsgdialog_ok=34</TD>
</TR><TR ALIGN='LEFT'>   <TD>commandsinput_type_tcl_command_here=1</TD>
   <TD>coretreetablepanel_core_tree_table=34</TD>
   <TD>createsrcfiledialog_file_name=9</TD>
   <TD>customizecoredialog_documentation=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>customizecoredialog_ip_location=1</TD>
   <TD>customizecoredialog_switch_to_defaults=1</TD>
   <TD>debugnetstreepanel_debug_nets_tree_table=17</TD>
   <TD>debugview_debug_cores_tree_table=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>debugview_tabbed_pane=1</TD>
   <TD>debugwizard_chipscope_tree_table=25</TD>
   <TD>debugwizard_disconnect_all_nets_and_remove_debug=2</TD>
   <TD>debugwizard_find_nets_to_add=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>debugwizard_find_results=1</TD>
   <TD>debugwizard_netlist_view=5</TD>
   <TD>debugwizard_remove_nets=2</TD>
   <TD>debugwizard_sample_of_data_depth=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>debugwizard_select_clock_domain=10</TD>
   <TD>debugwizard_set_probe_type=1</TD>
   <TD>exprunmenu_set_incremental_compile=2</TD>
   <TD>expruntreepanel_exp_run_tree_table=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>filesetpanel_file_set_panel_tree=945</TD>
   <TD>filesetpanel_messages=2</TD>
   <TD>filterednetswarningdialog_ok=2</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=312</TD>
</TR><TR ALIGN='LEFT'>   <TD>graphicalview_zoom_fit=73</TD>
   <TD>graphicalview_zoom_in=56</TD>
   <TD>graphicalview_zoom_out=1</TD>
   <TD>hacgccoefiledialog_help=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>hacgccoefiledialog_save=8</TD>
   <TD>hacgccoefiledialog_validate=17</TD>
   <TD>hacgccoefilewidget_browse=14</TD>
   <TD>hacgccoefilewidget_edit=16</TD>
</TR><TR ALIGN='LEFT'>   <TD>hacgctabbedpane_tabbed_pane=1</TD>
   <TD>hardwarecfgmemproppanels_specify_configuration_memory_part=2</TD>
   <TD>hardwarecfgmemproppanels_specify_configuration_memory_programming=1</TD>
   <TD>hardwaredashboardview_cell_name_for_debug_core=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>hardwareilawaveformview_run_trigger_for_this_ila_core=3</TD>
   <TD>hardwareilawaveformview_run_trigger_immediate_for_this_ila_core=31</TD>
   <TD>hardwareilawaveformview_stop_trigger_for_this_ila_core=5</TD>
   <TD>hardwareilawaveformview_toggle_auto_re_trigger_mode=13</TD>
</TR><TR ALIGN='LEFT'>   <TD>hardwaretreepanel_hardware_tree_table=201</TD>
   <TD>hjfilechooserhelpers_delete_selected_file_or_folder=2</TD>
   <TD>hjfilechooserrecentlistpreview_recent_directories=8</TD>
   <TD>hpopuptitle_close=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>htree_collapse_all=1</TD>
   <TD>incrementalcompilepanel_select_checkpoint_file_to_use_as=3</TD>
   <TD>labtoolsmenu_1s=2</TD>
   <TD>labtoolsmenu_jtag_scan_rate=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>logmonitor_monitor=7</TD>
   <TD>logpanel_log_navigator=1</TD>
   <TD>mainmenumgr_design_hubs=2</TD>
   <TD>mainmenumgr_edit=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_export=6</TD>
   <TD>mainmenumgr_file=40</TD>
   <TD>mainmenumgr_floorplanning=3</TD>
   <TD>mainmenumgr_flow=14</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_help=12</TD>
   <TD>mainmenumgr_import=4</TD>
   <TD>mainmenumgr_io_planning=3</TD>
   <TD>mainmenumgr_open_recent_file=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_open_recent_project=48</TD>
   <TD>mainmenumgr_report=61</TD>
   <TD>mainmenumgr_timing=3</TD>
   <TD>mainmenumgr_tools=132</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_unselect_type=2</TD>
   <TD>mainmenumgr_view=23</TD>
   <TD>mainmenumgr_window=62</TD>
   <TD>maintoolbarmgr_open=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>maintoolbarmgr_run=1</TD>
   <TD>mainwinmenumgr_layout=13</TD>
   <TD>mainwintoolbarmgr_select_or_save_window_layout=1</TD>
   <TD>msgtreepanel_message_view_tree=97</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgview_clear_messages_resulting_from_user_executed=2</TD>
   <TD>msgview_critical_warnings=1</TD>
   <TD>msgview_information_messages=4</TD>
   <TD>msgview_warning_messages=19</TD>
</TR><TR ALIGN='LEFT'>   <TD>navigabletimingreporttab_timing_report_navigation_tree=12</TD>
   <TD>netlisttreeview_netlist_tree=80</TD>
   <TD>pacommandnames_add_config_memory=6</TD>
   <TD>pacommandnames_auto_connect_target=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_auto_update_hier=12</TD>
   <TD>pacommandnames_boot_device=5</TD>
   <TD>pacommandnames_create_hardware_dashboards=9</TD>
   <TD>pacommandnames_fileset_window=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_goto_netlist_design=9</TD>
   <TD>pacommandnames_hardware_window=1</TD>
   <TD>pacommandnames_mark_debug_net=1</TD>
   <TD>pacommandnames_open_hardware_manager=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_open_project=1</TD>
   <TD>pacommandnames_open_recent_target=46</TD>
   <TD>pacommandnames_program_config_memory=27</TD>
   <TD>pacommandnames_program_fpga=33</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_refresh_target=2</TD>
   <TD>pacommandnames_run_bitgen=28</TD>
   <TD>pacommandnames_save_project_as=4</TD>
   <TD>pacommandnames_select_area=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_set_as_top=6</TD>
   <TD>pacommandnames_show_product_guide=1</TD>
   <TD>pacommandnames_show_product_webpage=1</TD>
   <TD>pacommandnames_simulation_relaunch=37</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_run_behavioral=34</TD>
   <TD>pacommandnames_src_replace_file=2</TD>
   <TD>pacommandnames_stop_trigger=5</TD>
   <TD>pacommandnames_trigger_immediate=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_unmark_debug_net=1</TD>
   <TD>pacommandnames_write_config_memory_file=48</TD>
   <TD>pacommandnames_zoom_fit=2</TD>
   <TD>paviews_dashboard=21</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_device=2</TD>
   <TD>paviews_schematic=2</TD>
   <TD>pickclockdomainnetdialog_clock_domain_nets_tree=8</TD>
   <TD>probesview_probes_tree=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>programcfgmemdialog_blank_check=5</TD>
   <TD>programcfgmemdialog_contents_of_configuration_file=11</TD>
   <TD>programcfgmemdialog_memory_device=1</TD>
   <TD>programcfgmemdialog_specify_prm_file=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>programdebugtab_open_recently_opened_target=22</TD>
   <TD>programdebugtab_open_target=2</TD>
   <TD>programdebugtab_program_device=6</TD>
   <TD>programfpgadialog_program=39</TD>
</TR><TR ALIGN='LEFT'>   <TD>programfpgadialog_specify_bitstream_file=12</TD>
   <TD>programfpgadialog_specify_debug_probes_file=2</TD>
   <TD>progressdialog_background=11</TD>
   <TD>progressdialog_cancel=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>projectnamechooser_project_name=5</TD>
   <TD>projectsettingssimulationpanel_tabbed_pane=1</TD>
   <TD>projectsummarydrcpanel_open_drc_report=2</TD>
   <TD>projectsummarypowerpanel_tabbed_pane=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>projectsummarytimingpanel_project_summary_timing_panel_tabbed=6</TD>
   <TD>projectsummaryutilizationgadget_project_summary_utilization_gadget_tabbed=2</TD>
   <TD>projecttab_reload=10</TD>
   <TD>rdicommands_custom_commands=14</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_delete=4</TD>
   <TD>rdicommands_properties=8</TD>
   <TD>rdicommands_settings=5</TD>
   <TD>rdiviews_waveform_viewer=226</TD>
</TR><TR ALIGN='LEFT'>   <TD>removesourcesdialog_also_delete=3</TD>
   <TD>rungadget_run_gadget_tabbed_pane=8</TD>
   <TD>rungadget_show_warning_and_error_messages_in_messages=2</TD>
   <TD>saveprojectutils_save=16</TD>
</TR><TR ALIGN='LEFT'>   <TD>selectmenu_highlight=5</TD>
   <TD>selectmenu_mark=3</TD>
   <TD>settingsdialog_options_tree=10</TD>
   <TD>settingsdialog_project_tree=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>simpleoutputproductdialog_generate_output_products_immediately=23</TD>
   <TD>simpleoutputproductdialog_synthesize_all_ip_including_ip_contained=3</TD>
   <TD>simpleoutputproductdialog_synthesize_design_globally=3</TD>
   <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchooserpanel_create_file=8</TD>
   <TD>srcmenu_ip_hierarchy=15</TD>
   <TD>stalerundialog_run_synthesis=2</TD>
   <TD>statemonitor_reset_run=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>syntheticagettingstartedview_recent_projects=17</TD>
   <TD>syntheticastatemonitor_cancel=4</TD>
   <TD>tclconsoleview_clear_all_output_in_tcl_console=3</TD>
   <TD>tclconsoleview_tcl_console_code_editor=148</TD>
</TR><TR ALIGN='LEFT'>   <TD>tclobjecttreetable_treetable=5</TD>
   <TD>triggerstatuspanel_run_trigger_for_this_ila_core=2</TD>
   <TD>triggerstatuspanel_run_trigger_immediate_for_this_ila_core=21</TD>
   <TD>triggerstatuspanel_toggle_auto_re_trigger_mode=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>waveformnametree_waveform_name_tree=336</TD>
   <TD>waveformview_add=5</TD>
   <TD>waveformview_goto_time_0=2</TD>
   <TD>writecfgmemfiledialog_add_new_file_option_panel=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>writecfgmemfiledialog_custom_memory_size=6</TD>
   <TD>writecfgmemfiledialog_disable_bit_swapping=9</TD>
   <TD>writecfgmemfiledialog_format=16</TD>
   <TD>writecfgmemfiledialog_interface=22</TD>
</TR><TR ALIGN='LEFT'>   <TD>writecfgmemfiledialog_load_bitstream_files=7</TD>
   <TD>writecfgmemfiledialog_load_data_files=6</TD>
   <TD>writecfgmemfiledialog_memory_part=7</TD>
   <TD>writecfgmemfiledialog_overwrite=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>writecfgmemfiledialog_part_chooser=10</TD>
   <TD>writecfgmemfiledialog_remove_this_file_option_panel=2</TD>
   <TD>writecfgmemfiledialog_specify_bitfile_filename=8</TD>
   <TD>writecfgmemfiledialog_specify_configuration_filename=28</TD>
</TR><TR ALIGN='LEFT'>   <TD>writecfgmemfiledialog_specify_datafile_filename=2</TD>
   <TD>writecfgmemfiledialog_write_checksum=7</TD>
   <TD>xpg_ipsymbol_show_disabled_ports=4</TD>
   <TD>xpg_tabbedpane_tabbed_pane=10</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addcfgmem=15</TD>
   <TD>addsources=10</TD>
   <TD>autoconnecttarget=2</TD>
   <TD>bootdevice=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>coreview=5</TD>
   <TD>createhardwaredashboards=1</TD>
   <TD>customizecore=10</TD>
   <TD>debugwizardcmdhandler=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>editdelete=4</TD>
   <TD>editproperties=7</TD>
   <TD>launchprogramfpga=40</TD>
   <TD>markdebug=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>openexistingreport=1</TD>
   <TD>openhardwaredashboard=1</TD>
   <TD>openhardwaremanager=56</TD>
   <TD>openproject=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>openrecenttarget=19</TD>
   <TD>programcfgmem=36</TD>
   <TD>programdevice=41</TD>
   <TD>recustomizecore=26</TD>
</TR><TR ALIGN='LEFT'>   <TD>refreshtarget=2</TD>
   <TD>runbitgen=32</TD>
   <TD>runimplementation=35</TD>
   <TD>runsynthesis=41</TD>
</TR><TR ALIGN='LEFT'>   <TD>runtrigger=5</TD>
   <TD>runtriggerimmediate=52</TD>
   <TD>saveprojectas=4</TD>
   <TD>setjtagscanrate=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>settopnode=6</TD>
   <TD>showproductguide=1</TD>
   <TD>showproductwebpage=1</TD>
   <TD>showview=21</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationrelaunch=37</TD>
   <TD>simulationrun=34</TD>
   <TD>stoptrigger=10</TD>
   <TD>tclfind=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>toggleselectareamode=1</TD>
   <TD>toolssettings=10</TD>
   <TD>unmarkdebug=1</TD>
   <TD>updatesourcefiles=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewlayoutcmd=1</TD>
   <TD>viewtaskimplementation=3</TD>
   <TD>viewtaskrtlanalysis=6</TD>
   <TD>viewtasksynthesis=16</TD>
</TR><TR ALIGN='LEFT'>   <TD>writecfgmemfile=47</TD>
   <TD>zoomfit=2</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=28</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=17</TD>
   <TD>export_simulation_ies=17</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=17</TD>
   <TD>export_simulation_questa=17</TD>
   <TD>export_simulation_riviera=17</TD>
   <TD>export_simulation_vcs=17</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=17</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=105</TD>
   <TD>simulator_language=Verilog</TD>
   <TD>srcsetcount=12</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=5</TD>
   <TD>totalsynthesisruns=5</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
    <TD>carry4=14</TD>
    <TD>fdce=183</TD>
    <TD>fdpe=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=80</TD>
    <TD>gnd=17</TD>
    <TD>ibuf=3</TD>
    <TD>ibufds=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1=56</TD>
    <TD>lut2=46</TD>
    <TD>lut3=63</TD>
    <TD>lut4=49</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5=83</TD>
    <TD>lut6=644</TD>
    <TD>mmcme2_adv=1</TD>
    <TD>muxf7=157</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf8=53</TD>
    <TD>obuf=35</TD>
    <TD>obuft=1</TD>
    <TD>ramb36e1=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=15</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
    <TD>carry4=14</TD>
    <TD>fdce=183</TD>
    <TD>fdpe=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=80</TD>
    <TD>gnd=17</TD>
    <TD>ibuf=3</TD>
    <TD>ibufds=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1=56</TD>
    <TD>lut2=46</TD>
    <TD>lut3=63</TD>
    <TD>lut4=49</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5=83</TD>
    <TD>lut6=644</TD>
    <TD>mmcme2_adv=1</TD>
    <TD>muxf7=157</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf8=53</TD>
    <TD>obuf=35</TD>
    <TD>obuft=1</TD>
    <TD>ramb36e1=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=15</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=5</TD>
    <TD>bram_ports_newly_gated=2</TD>
    <TD>bram_ports_total=16</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=2066</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=170</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>blk_mem_gen_v8_3_6/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addra_width=13</TD>
    <TD>c_addrb_width=13</TD>
    <TD>c_algorithm=1</TD>
    <TD>c_axi_id_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_slave_type=0</TD>
    <TD>c_axi_type=1</TD>
    <TD>c_byte_size=9</TD>
    <TD>c_common_clk=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_count_18k_bram=0</TD>
    <TD>c_count_36k_bram=3</TD>
    <TD>c_ctrl_ecc_algo=NONE</TD>
    <TD>c_default_data=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_disable_warn_bhv_coll=0</TD>
    <TD>c_disable_warn_bhv_range=0</TD>
    <TD>c_elaboration_dir=./</TD>
    <TD>c_en_deepsleep_pin=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_ecc_pipe=0</TD>
    <TD>c_en_rdaddra_chg=0</TD>
    <TD>c_en_rdaddrb_chg=0</TD>
    <TD>c_en_safety_ckt=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_shutdown_pin=0</TD>
    <TD>c_en_sleep_pin=0</TD>
    <TD>c_enable_32bit_address=0</TD>
    <TD>c_est_power_summary=Estimated Power for IP     _     4.62695 mW</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=kintex7</TD>
    <TD>c_has_axi_id=0</TD>
    <TD>c_has_ena=0</TD>
    <TD>c_has_enb=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_injecterr=0</TD>
    <TD>c_has_mem_output_regs_a=1</TD>
    <TD>c_has_mem_output_regs_b=0</TD>
    <TD>c_has_mux_output_regs_a=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_mux_output_regs_b=0</TD>
    <TD>c_has_regcea=0</TD>
    <TD>c_has_regceb=0</TD>
    <TD>c_has_rsta=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_rstb=0</TD>
    <TD>c_has_softecc_input_regs_a=0</TD>
    <TD>c_has_softecc_output_regs_b=0</TD>
    <TD>c_init_file=ipath_generator.mem</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_init_file_name=[user-defined]</TD>
    <TD>c_inita_val=0</TD>
    <TD>c_initb_val=0</TD>
    <TD>c_interface_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_load_init_file=1</TD>
    <TD>c_mem_type=3</TD>
    <TD>c_mux_pipeline_stages=0</TD>
    <TD>c_prim_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_depth_a=7200</TD>
    <TD>c_read_depth_b=7200</TD>
    <TD>c_read_width_a=12</TD>
    <TD>c_read_width_b=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rst_priority_a=CE</TD>
    <TD>c_rst_priority_b=CE</TD>
    <TD>c_rstram_a=0</TD>
    <TD>c_rstram_b=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sim_collision_check=ALL</TD>
    <TD>c_use_bram_block=0</TD>
    <TD>c_use_byte_wea=0</TD>
    <TD>c_use_byte_web=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_default_data=0</TD>
    <TD>c_use_ecc=0</TD>
    <TD>c_use_softecc=0</TD>
    <TD>c_use_uram=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wea_width=1</TD>
    <TD>c_web_width=1</TD>
    <TD>c_write_depth_a=7200</TD>
    <TD>c_write_depth_b=7200</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_write_mode_a=WRITE_FIRST</TD>
    <TD>c_write_mode_b=WRITE_FIRST</TD>
    <TD>c_write_width_a=12</TD>
    <TD>c_write_width_b=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_xdevicefamily=kintex7</TD>
    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=blk_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2017.1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=VERILOG</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=8.3</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>blk_mem_gen_v8_3_6/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addra_width=13</TD>
    <TD>c_addrb_width=13</TD>
    <TD>c_algorithm=1</TD>
    <TD>c_axi_id_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_slave_type=0</TD>
    <TD>c_axi_type=1</TD>
    <TD>c_byte_size=9</TD>
    <TD>c_common_clk=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_count_18k_bram=0</TD>
    <TD>c_count_36k_bram=3</TD>
    <TD>c_ctrl_ecc_algo=NONE</TD>
    <TD>c_default_data=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_disable_warn_bhv_coll=0</TD>
    <TD>c_disable_warn_bhv_range=0</TD>
    <TD>c_elaboration_dir=./</TD>
    <TD>c_en_deepsleep_pin=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_ecc_pipe=0</TD>
    <TD>c_en_rdaddra_chg=0</TD>
    <TD>c_en_rdaddrb_chg=0</TD>
    <TD>c_en_safety_ckt=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_shutdown_pin=0</TD>
    <TD>c_en_sleep_pin=0</TD>
    <TD>c_enable_32bit_address=0</TD>
    <TD>c_est_power_summary=Estimated Power for IP     _     4.62695 mW</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=kintex7</TD>
    <TD>c_has_axi_id=0</TD>
    <TD>c_has_ena=0</TD>
    <TD>c_has_enb=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_injecterr=0</TD>
    <TD>c_has_mem_output_regs_a=1</TD>
    <TD>c_has_mem_output_regs_b=0</TD>
    <TD>c_has_mux_output_regs_a=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_mux_output_regs_b=0</TD>
    <TD>c_has_regcea=0</TD>
    <TD>c_has_regceb=0</TD>
    <TD>c_has_rsta=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_rstb=0</TD>
    <TD>c_has_softecc_input_regs_a=0</TD>
    <TD>c_has_softecc_output_regs_b=0</TD>
    <TD>c_init_file=qpath_generator.mem</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_init_file_name=[user-defined]</TD>
    <TD>c_inita_val=0</TD>
    <TD>c_initb_val=0</TD>
    <TD>c_interface_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_load_init_file=1</TD>
    <TD>c_mem_type=3</TD>
    <TD>c_mux_pipeline_stages=0</TD>
    <TD>c_prim_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_read_depth_a=7200</TD>
    <TD>c_read_depth_b=7200</TD>
    <TD>c_read_width_a=12</TD>
    <TD>c_read_width_b=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rst_priority_a=CE</TD>
    <TD>c_rst_priority_b=CE</TD>
    <TD>c_rstram_a=0</TD>
    <TD>c_rstram_b=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_sim_collision_check=ALL</TD>
    <TD>c_use_bram_block=0</TD>
    <TD>c_use_byte_wea=0</TD>
    <TD>c_use_byte_web=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_default_data=0</TD>
    <TD>c_use_ecc=0</TD>
    <TD>c_use_softecc=0</TD>
    <TD>c_use_uram=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wea_width=1</TD>
    <TD>c_web_width=1</TD>
    <TD>c_write_depth_a=7200</TD>
    <TD>c_write_depth_b=7200</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_write_mode_a=WRITE_FIRST</TD>
    <TD>c_write_mode_b=WRITE_FIRST</TD>
    <TD>c_write_width_a=12</TD>
    <TD>c_write_width_b=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_xdevicefamily=kintex7</TD>
    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=blk_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2017.1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=VERILOG</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=8.3</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v5_4_0_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=5.000</TD>
    <TD>clkin2_period=10.0</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=clk_wiz_0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=1</TD>
    <TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=false</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=true</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>labtools_ila_v6_00_a/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>all_probe_same_mu=true</TD>
    <TD>all_probe_same_mu_cnt=1</TD>
    <TD>c_adv_trigger=false</TD>
    <TD>c_data_depth=1024</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_strg_qual=false</TD>
    <TD>c_input_pipe_stages=0</TD>
    <TD>c_num_of_probes=3</TD>
    <TD>c_probe0_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_probe0_width=12</TD>
    <TD>c_probe1_type=0</TD>
    <TD>c_probe1_width=12</TD>
    <TD>c_probe2_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_probe2_width=12</TD>
    <TD>c_trigin_en=0</TD>
    <TD>c_trigout_en=0</TD>
    <TD>component_name=u_ila_0_CV</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>labtools_xsdbm_v3_00_a/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_bscan_mode=false</TD>
    <TD>c_bscan_mode_with_core=false</TD>
    <TD>c_clk_input_freq_hz=300000000</TD>
    <TD>c_en_bscanid_vec=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_enable_clk_divider=false</TD>
    <TD>c_num_bscan_master_ports=0</TD>
    <TD>c_two_prim_mode=false</TD>
    <TD>c_use_ext_bscan=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_user_scan_chain=1</TD>
    <TD>c_xsdb_num_slaves=1</TD>
    <TD>component_name=dbg_hub_CV</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>cfgbvs-1=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=4</TD>
    <TD>bufgctrl_util_percentage=12.50</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=168</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=40</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=20</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=40</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=10</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=1</TD>
    <TD>mmcme2_adv_util_percentage=10.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=10</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=840</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_i_dci=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_i_dci_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hstl_ii_dci=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_dci_18=0</TD>
    <TD>diff_hstl_ii_t_dci=0</TD>
    <TD>diff_hstl_ii_t_dci_18=0</TD>
    <TD>diff_hsul_12=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hsul_12_dci=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl12=0</TD>
    <TD>diff_sstl12_dci=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl12_t_dci=0</TD>
    <TD>diff_sstl135=0</TD>
    <TD>diff_sstl135_dci=0</TD>
    <TD>diff_sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_t_dci=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_dci=0</TD>
    <TD>diff_sstl15_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl15_t_dci=0</TD>
    <TD>diff_sstl18_i=0</TD>
    <TD>diff_sstl18_i_dci=0</TD>
    <TD>diff_sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii_dci=0</TD>
    <TD>diff_sstl18_ii_t_dci=0</TD>
    <TD>hslvdci_15=0</TD>
    <TD>hslvdci_18=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_i=0</TD>
    <TD>hstl_i_12=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_i_dci=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_i_dci_18=0</TD>
    <TD>hstl_ii=0</TD>
    <TD>hstl_ii_18=0</TD>
    <TD>hstl_ii_dci=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_dci_18=0</TD>
    <TD>hstl_ii_t_dci=0</TD>
    <TD>hstl_ii_t_dci_18=0</TD>
    <TD>hsul_12=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hsul_12_dci=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=1</TD>
    <TD>lvcmos18=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos25=1</TD>
    <TD>lvcmos33=0</TD>
    <TD>lvdci_15=0</TD>
    <TD>lvdci_18=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvdci_dv2_15=0</TD>
    <TD>lvdci_dv2_18=0</TD>
    <TD>lvds=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl12=0</TD>
    <TD>sstl12_dci=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl12_t_dci=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_dci=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl135_t_dci=0</TD>
    <TD>sstl15=0</TD>
    <TD>sstl15_dci=0</TD>
    <TD>sstl15_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15_t_dci=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_i_dci=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl18_ii_dci=0</TD>
    <TD>sstl18_ii_t_dci=0</TD>
    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=445</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=7.5</TD>
    <TD>block_ram_tile_util_percentage=1.69</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=890</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=1</TD>
    <TD>ramb18_util_percentage=0.11</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18e1_only_used=1</TD>
    <TD>ramb36_fifo_available=445</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_util_percentage=1.57</TD>
    <TD>ramb36e1_only_used=7</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_functional_category=Others</TD>
    <TD>bscane2_used=1</TD>
    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=46</TD>
    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=358</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=43</TD>
    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=1655</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=14</TD>
    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibufds_functional_category=IO</TD>
    <TD>ibufds_used=1</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=37</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=158</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=264</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=236</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=266</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=1025</TD>
    <TD>mmcme2_adv_functional_category=Clock</TD>
    <TD>mmcme2_adv_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=160</TD>
    <TD>muxf8_functional_category=MuxFx</TD>
    <TD>muxf8_used=53</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=35</TD>
    <TD>obuft_functional_category=IO</TD>
    <TD>obuft_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18e1_functional_category=Block Memory</TD>
    <TD>ramb18e1_used=1</TD>
    <TD>ramb36e1_functional_category=Block Memory</TD>
    <TD>ramb36e1_used=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramd32_functional_category=Distributed Memory</TD>
    <TD>ramd32_used=36</TD>
    <TD>rams32_functional_category=Distributed Memory</TD>
    <TD>rams32_used=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>srl16e_functional_category=Distributed Memory</TD>
    <TD>srl16e_used=92</TD>
    <TD>srlc16e_functional_category=Distributed Memory</TD>
    <TD>srlc16e_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>srlc32e_functional_category=Distributed Memory</TD>
    <TD>srlc32e_used=76</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=101900</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=160</TD>
    <TD>f7_muxes_util_percentage=0.16</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=50950</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=53</TD>
    <TD>f8_muxes_util_percentage=0.10</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=24</TD>
    <TD>lut_as_logic_available=203800</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=1779</TD>
    <TD>lut_as_logic_util_percentage=0.87</TD>
    <TD>lut_as_memory_available=64000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=126</TD>
    <TD>lut_as_memory_util_percentage=0.20</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=102</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=407600</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=2070</TD>
    <TD>register_as_flip_flop_util_percentage=0.51</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=407600</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=203800</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=1905</TD>
    <TD>slice_luts_util_percentage=0.93</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=407600</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=2070</TD>
    <TD>slice_registers_util_percentage=0.51</TD>
</TR><TR ALIGN='LEFT'>    <TD>fully_used_lut_ff_pairs_fixed=0.51</TD>
    <TD>fully_used_lut_ff_pairs_used=105</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=24</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=203800</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=1779</TD>
    <TD>lut_as_logic_util_percentage=0.87</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=64000</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=126</TD>
    <TD>lut_as_memory_util_percentage=0.20</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=102</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=102</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_used=480</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=480</TD>
    <TD>lut_ff_pairs_with_one_unused_lut_output_used=562</TD>
    <TD>lut_flip_flop_pairs_available=203800</TD>
    <TD>lut_flip_flop_pairs_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_used=709</TD>
    <TD>lut_flip_flop_pairs_util_percentage=0.35</TD>
    <TD>slice_available=50950</TD>
    <TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_used=822</TD>
    <TD>slice_util_percentage=1.61</TD>
    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=446</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=376</TD>
    <TD>unique_control_sets_used=138</TD>
    <TD>using_o5_and_o6_fixed=138</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=68</TD>
    <TD>using_o5_output_only_fixed=68</TD>
    <TD>using_o5_output_only_used=3</TD>
    <TD>using_o6_output_only_fixed=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=31</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=1</TD>
    <TD>bscane2_util_percentage=25.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_fixed=0</TD>
    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>actual_expansions=4662706</TD>
    <TD>bogomips=0</TD>
    <TD>bram18=1</TD>
    <TD>bram36=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufg=0</TD>
    <TD>bufr=0</TD>
    <TD>congestion_level=0</TD>
    <TD>ctrls=138</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsp=0</TD>
    <TD>effort=2</TD>
    <TD>estimated_expansions=2602122</TD>
    <TD>ff=2070</TD>
</TR><TR ALIGN='LEFT'>    <TD>global_clocks=4</TD>
    <TD>high_fanout_nets=2</TD>
    <TD>iob=41</TD>
    <TD>lut=2020</TD>
</TR><TR ALIGN='LEFT'>    <TD>movable_instances=4830</TD>
    <TD>nets=5133</TD>
    <TD>pins=27801</TD>
    <TD>pll=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>router_runtime=0.000000</TD>
    <TD>router_timing_driven=1</TD>
    <TD>threads=2</TD>
    <TD>timing_constraints_exist=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7k325tffg900-2</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=ad9361_tx_top</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:57s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=527.227MB</TD>
    <TD>memory_peak=806.809MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=behavioral</TD>
    <TD>-sim_type=default::</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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